1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device and its semiconductor memory arrays and, more particularly, to a stack-gate flash memory cell structure and its contactless flash memory arrays.
2. Description of Related Art
The stack-gate flash memory cell is known to be a one-transistor cell, in which the gate length of a cell can be defined by using a minimum-feature-size (F) of technology used. Therefore, the stack-gate flash memory cell is often used in existing high-density memory system.
FIG. 1A shows a typical schematic structure of a stack-gate flash memory cell, in which a gate-stack including a control-gate layer (CG) 104a, an intergate-dielectric layer 103a, a floating-gate layer (FG) 102a, and a tunneling-dielectric layer 101a is patterned and formed on a semiconductor substrate 100; a double-diffused source structure including a shallow heavily-doped source diffusion region 106a being formed within a deeper lightly-doped source diffusion region 105a is formed in the source side of the gate-stack; and a shallow heavily-doped drain diffusion region 106a is formed in the drain side of the gate-stack. The double-diffused source structure is mainly used to eliminate the band-to-band tunneling effect during the erasing operation and may offer a larger overlapping area for the source-side erase. The shallow heavily-doped drain diffusion region 106a is mainly used to tailor a drain electric field for hot-electron generation during the programming operation. The asymmetric source/drain diffusion structure shown in FIG. 1A can be used to implement a NOR-type flash memory array.
FIG. 1B shows another typical schematic structure of a stack-gate flash memory cell, in which a gate-stack is also patterned and formed in a semiconductor substrate 100, and a symmetrical source/drain diffusion structure having a heavily-doped source/drain diffusion region 105a/105b is formed in both sides of the gate-stack. The symmetrical source/drain diffusion structure is mainly used to implement a NAND-type flash memory array.
It is clearly seen from FIG. 1A and FIG. 1B that as the gate length of the gate-stack is scaled, the punch-through voltage of a stack-gate flash memory cell which is proportional to the square of the gate length is reduced drastically. The reduction of the punch-through voltage becomes a major concern for FIG. 1A because a moderately high drain voltage is in general needed for programming using hot-electron injection. Similarly, the junction depth of the source/drain diffusion regions must also be scaled accordingly, the erasing area using either the source-side erase or the substrate erase becomes smaller and the erasing speed becomes slower. Moreover, the read speed of a NAND-type array will be drastically reduced due to a higher parasitic source/drain series resistance of a shallow common source/drain diffusion region.
It is, therefore, a major objective of the present invention to offer an efficient punch-through stop structure for a stack-gate flash memory cell.
It is another objective of the present invention to offer a highly conductive bus line or island for shallow source/drain diffusion regions to improve the contact resistance and the contact integrity of a flash memory array.
It is further objective of the present invention to offer a contactless structure for different flash memory arrays.
A stack-gate flash memory cell structure and its contactless flash memory arrays are disclosed by the present invention. The stack-gate flash memory cell structure of the present invention comprises a source diffusion region and a drain diffusion region being separately or simultaneously formed in each side portion of a gate-stack region; a floating-gate structure with a thinner floating-gate layer being formed in a central portion by using a pair of second sidewall dielectric spacers being formed over inner sidewalls of a gate-stack; an implanted region comprising a shallow implant region for threshold-voltage adjustment and a deeper implant region for forming a punch-through stop being formed in a central portion of a channel between the pair of second sidewall dielectric spacers; a highly conductive control-gate structure spaced with an intergate-dielectric layer being formed over the floating-gate structure. The stack-gate flash memory cell structure of the present invention is used to implement two different types of contactless flash memory array: a contactless NOR-type flash memory array and a contactless parallel common-source/drain bit-line flash memory array.
The contactless NOR-type flash memory array of the present invention comprises a plurality of gate-stacks being formed over a shallow-trench-isolation (STI) structure having a plurality of parallel shallow-trench-isolation regions and a plurality of active regions formed alternately in a semiconductor substrate of a first conductive type, wherein each of the plurality of gate-stacks comprises: a plurality of floating-gate structures being alternately formed in the plurality of active regions with an elongated control-gate conductive layer spaced by an intergate-dielectric layer being formed over the plurality of floating-gate structures and a plurality of first raised field-oxide layers to act as a word line, a plurality of implanted regions of said first conductivity type being formed in central portions of the plurality of active regions for threshold-voltage adjustment and forming punch-through stops; a plurality of common-source conductive bus lines being formed over a plurality of first flat beds between first sidewall dielectric spacers with each of the plurality of first flat beds being alternately formed by a common-source diffusion region of a second conductivity type and a third raised field-oxide layer; a plurality of planarized common-drain conductive islands being formed on a plurality of common-drain diffusion regions of the second conductivity type between another first sidewall dielectric spacers formed over a portion of a plurality of second flat beds with each of the plurality of second flat beds being alternately formed a common-drain diffusion region of the second conductivity type and a third raised field-oxide layer; and a plurality of metal bit-lines integrated with the plurality of planarized common-drain conductive islands being formed transversely to the plurality of gate-stacks.
The contactless parallel common-source/drain bit-line flash memory array of the present invention comprises a plurality of gate-stacks being formed over a shallow-trench-isolation structure having a plurality of parallel STI regions and a plurality of active regions formed alternately on a semiconductor substrate of a first conductivity type, wherein each of the plurality of gate-stacks comprises: a plurality of floating-gate structures being alternately formed in the plurality of active regions with a plurality of planarized control-gate conductive islands spaced by an intergate-dielectric layer being formed over the plurality of floating-gate structures, a plurality of implanted regions of the first conductivity type being formed in central portions of the plurality of active regions for threshold-voltage adjustment and forming punch-through stops; a plurality of common-source/drain conductive bit-lines being formed over a plurality of first/second flat beds between first sidewall dielectric spacers with each of the plurality of first/second flat beds being alternately formed by a common-source/drain diffusion region of a second conductivity type and a third raised field-oxide layer; and a plurality of metal word-lines integrated with the plurality of planarized control-gate conductive islands being formed transversely to the plurality of common-source/drain conductive bit-lines.